Research on the maritime communication cryptographic chip’s compiler optimization
In the process of ocean development, the technology for maritime communication system is a hot research field, of which information security is vital for the normal operation of the whole system, and that is also one of the difficulties in the research of maritime communication system. In this paper, a kind of maritime communication cryptographic SOC(system on chip) is introduced, and its compiler framework is put forward through analysis of working mode and problems faced by compiler front end. Then, a loop unrolling factor calculating algorithm based on queue theory, named UFBOQ (unrolling factor based on queue), is proposed to make parallel optimization in the compiler frontend with consideration of the instruction memory capacity limit. Finally, the scalar replacement method is used to optimize unrolled code to solve the memory access latency on the parallel computing efficiency, for continuous data storage characteristics of cryptographic algorithm. The UFBOQ algorithm and scalar replacement prove effective and appropriate, of which the effect achieves the linear speedup
- 1. RWL Coutinho, A Boukerche， LFM Vieira, AAF Loureiro. A novel void node recovery paradigm for longterm underwater sensor networks. Ad Hoc Networks, Vol. 34, No.C , pp.144-156, 2015.
- 2. MR Bharamagoudra, SKS Manvi. Deployment Scheme for Enhancing Coverage and Connectivity in Underwater Acoustic Sensor Networks. Wireless Personal Communications, Vol.89, No.4, pp.1265-1293,2016.
- 3. J Xu, A Lin, X Yu et al. Underwater Laser Communication Using an OFDM-Modulated 520-nm Laser Diode. IEEE Photonics Technology Letters,28 (20),pp.2133 - 2136, 2016.
- 4. C Specht. Accuracy and coverage of the modernized Polish Maritime differential GPS system.Advances in Space Research, Vol.47,No.2, pp.221-228,2011 .
- 5. G Dini, AL Duca. A Secure Communication Suite for Underwater Acoustic Sensor Networks.Sensors, Vol.12,No.11,pp. 15133-15158,2012.
- 6. K. akdemir, M. Dixon, et al. Breakthrough AES performance with Intel AES new Instructions. Whilte paper, June, 2010
- 7. J. burk, J. Mcdonald, et al. Architecture support for fast symmetric-key cryptography. Acm Sigplan Notices, Vol.35, No.11:178-189, 2000.
- 8. Wang Y, Ha Y. FPGA based 40.9-Gbit/s Masked AES with Area optimization for storage area network. Circuits & Systems II Express Briefs IEEE Tranaction on , Vol. 60, No.1, pp.36-40, 2013.
- 9. LI Wei, ZENG xiaoyang, NAN longmei. A Reconfigurable Block Cryptographic Processor Based on VLIW Architecture[J]. China Communication, Vol.13, No.1, pp. 91-98, 2016
- 10. Gao Fei，Li hongyan, Zhang Yongfu. Research on cipher coprocessor instruction level parallelism compiler, Application research of computers, Vol. 27, No.5, pp. 1633-1637,2010.
- 11. DAVID F. BACON, SUSAN L. GRAHAM, AND OLIVER J. SHARP. Compiler transformations for high-performance computing, Acm Computing Surveys, Vol. 26, No.4, pp. 345-420, 1994.